Conventional voltage regulators include those having a circuit configuration that consumes a large amount of current in order to improve power supply rejection ratio (PSRR), or ripple rejection, and load transient response and those having a circuit configuration whose current consumption is reduced because of no need for a high-speed response capability.
If an apparatus having an operating state where the apparatus operates with normal current consumption and a standby state such as a sleep mode where current consumption is reduced, such as a cellular phone, uses a voltage regulator having high response speed, the voltage regulator unnecessarily consumes a large amount of current in the standby state where no high response speed is required.
FIG. 1 is a diagram showing a circuit of a conventional voltage regulator. (See, for example, Patent Document 1.)
The voltage regulator of FIG. 1 includes a first error amplifier circuit 101 that consumes a large amount of current but operates at high speed, a second error amplifier circuit 102 whose current consumption is reduced, a reference voltage generator circuit 103, and a control unit 104.
Referring to FIG. 1, the first error amplifier circuit 101 and the second error amplifier circuit 102 have control signals input thereto from the control unit 104. Each of the first error amplifier circuit 101 and the second error amplifier circuit 102 exclusively starts or stops operating in response to the corresponding control signal. When the first error amplifier circuit 101 and the second error amplifier circuit 102 stop operating, their current consumption is reduced.
In the case of a heavy load operation mode outputting a large current from an output terminal 105, the first error amplifier circuit 101 is put into operation while the operation of the second error amplifier circuit 102 is stopped. As a result, an output transistor M101 is controlled by the first error amplifier circuit 101. Accordingly, the voltage regulator can operate at high speed although a large amount of current is consumed.
On the other hand, in the case of a light load operation mode outputting a small amount of current from the output terminal 105, the operation of the first error amplifier circuit 101 is stopped while the second error amplifier circuit 102 is put into operation. As a result, the output transistor M101 is controlled by the second error amplifier circuit 102. Accordingly, the voltage regulator can reduce current consumption.
In the voltage regulator of FIG. 1, however, since the number of output transistors is one, the output transistor M101 is large in device size so as to allow a maximum current at the time of the heavy load operation mode. Therefore, the output transistor M101 has a large gate capacitance for using the large-size transistor.
Controlling this output transistor M101 with the second error amplifier circuit 102 consuming a small amount of current results in a reduced transient response to a variation in output voltage. This causes a problem if the transient response characteristic is required at the time of the light load operation mode as well.
Therefore, in order to solve this problem, there is proposed a voltage regulator as shown in FIG. 2. (See, for example, Patent Document 2.)
The voltage regulator of FIG. 2 includes a first error amplifier circuit 111 that consumes a large amount of current but operates at high speed, and a second error amplifier circuit 112 whose current consumption is reduced. The first error amplifier circuit 111 controls the operation of a first output transistor M111, and the second error amplifier circuit 112 controls the operation of a second output transistor M112, which is remarkably smaller in device size than the first output transistor M111.
Each of the first error amplifier circuit 111 and the second error amplifier circuit 112 exclusively starts or stops operating in response to a control signal input to its control signal input. In FIG. 2, reference numeral 113 denotes a comparator circuit, reference numeral 114 denotes a reference voltage generator circuit, reference numeral 115 denotes a delay circuit, and reference numeral 116 denotes an OR circuit.
In the voltage regulator of FIG. 2, the first error amplifier circuit 111 is put into operation and the operation of the second error amplifier circuit 112 is stopped at the time of a heavy load operation mode with a large load current, and the operation of the first error amplifier circuit 111 is stopped and the second error amplifier circuit 112 is put into operation at the time of a light load operation mode with a small load current. That is, the second output transistor M112 having a small device size is used as an output transistor in the light load operation mode. This reduces the gate capacitance of the output transistor, so that it is possible to respond at high speed although the current consumption of the error amplifier circuit is reduced.
[Patent Document 1] Japanese Laid-Open Patent Application No. 2002-312043
[Patent Document 2] Japanese Patent No. 3710468
In the case of FIG. 2, however, one of the output transistors M111 and M112 is always kept from operating, which results in poor efficiency. Further, even the output transistor M112 that operates at the time of a small load current occupies a much larger space than common transistors, which causes an increase in chip size. Further, in the case of FIG. 2, two PMOS transistors M113 and M114 are required as transistors for detecting a load current, which causes the problem of an increase in circuit size.